1. Technical Field
The present invention relates to a semiconductor memory device including a plurality of memory cells, particularly, static-type memory cells in which thin film transistors (hereinafter, referred to as TFTS) are used as load elements, and to a method of manufacturing the same, and relates to a structure taking connections between thin film wiring layers and other wiring layers, and to a technique for realizing the structure.
2. Discussion
An example of a circuit configuration of a semiconductor memory including a plurality of static-type memory cells in which the TFTs are used as the load elements is shown in FIG. 18. Driver transistors which constitute the memory cells comprise N-channel FETs (N1 to N2n), and the load elements comprises P-channel TFTs (P1 to P2n). Here, source, drain and channel regions (hereinafter, referred to as bulk) of the TFTs are formed by a first polycrystalline silicon layer (hereinafter, referred to as PLYD), and gate electrodes of the TFTs are formed by a second polycrystalline silicon layer (hereinafter, referred to as PLYC). The source regions of the TFTs are connected to a power line 504 comprised of a metallic layer (hereinafter, referred to as AL), such as aluminum, through a power supplying line 500 comprised of the PLYD and a contact hole 502.
The PLYD, which forms the power supplying line 500, has a thickness of about 300 to 500 angstroms, and is very thin. For this reason, when the power line 504 is connected to the power supplying line 500 through the contact hole 502, there causes a problem in that the power line 504 penetrates to a lower layer.
As an example for solving the problem of penetration, there is a first background art disclosed in, for example, Japanese Patent Application Laid-Open No. 5-190686. In this background art, as shown in FIG. 19A, in condition where the penetration does not occur, a PLYD (514), which is the power supplying line of the memory cells, is connected to an AL (516), which is the power line, through the contact hole CNT, whereby it becomes possible to supply power to the memory cells. On the other hand, in this background art, a PLYC (512) is formed on transistors comprising lower layers or an insulating layer 510. And, the PLYD (514), which is the power supplying line of the memory cells, is connected to this PLYC (512) through a contact hole THLC. Therefore, even if the penetration due to the contact hole CNT occurs as shown in FIG. 19B, the PLYD (514) will be connected to the AL (516) through the PLYC (512) and the CNT. That is to say, by providing the PLYC (512), it becomes possible to supply power to the memory cells. Unlike the PLYD (514), which forms the bulk of the TFTs, the thickness of the PLYC (512) can be thickened. Therefore, it can be sufficiently used as an etching stopper layer (penetration preventing layer) at the time of etching of the CNT.
In addition, as a second background art for solving the problem of penetration, there are background arts disclosed in Japanese Patent Application Laid-Open Nos. 5-259408 and 6-5820. In these background arts, as indicated by G in FIG. 20, the PLYD (514), which supplies a current to the TFTs of the memory cells, and the AL (516) which is the power line are connected on the side surface. In addition, in order to prevent occurrence of the penetration, the PLYC (512), which is the etching stopper layer, is provided directly below the CNT. And, the PLYC (512) and PLYD (514) are not connected directly because they prevent diffusion of impurities from the PLYC, and the PLYC is floating (potential is not supplied).
The first and second background arts as described above include the technical problems described below.
In the first background art shown in FIGS. 19A, 19B, since the PLYD (514) is the bulk of the P-channel TFT, it is necessary to introduce P-type impurities when bringing into conduction to be a P-type polycrystalline silicon layer. On the other hand, in order to utilize the PLYC (512), which is the etching stopper layer, for the gate electrodes of the TFTS, and so on in the memory cell region, it is necessary to introduce N-type impurities to be an N-type polycrystalline silicon layer. Impurity concentrations of the PLYC (512) and the PLYD (514) are, for example, about 3.times.10.sup.20 /cm.sup.3, and 1.times.10.sup.20 /cm.sup.3, respectively, and the impurity concentration of the PLYC (512) is higher. Therefore, the N-type impurities contained in the PLYC (512) are diffused to the PLYD (514), so that a situation occurs in which a PN parasitic diode is formed on such a position indicated by F of FIG. 19A. Since power of the high potential side is supplied to the AL (516), the parasitic diode serves as a reverse-direction diode when supplying the power to the memory cells. For this reason, power supplying ability of the ON-state TFTs is limited by this reverse-direction parasitic diode to greatly affect properties of data retention of the memory cells and so on. As one technique for preventing generation of such parasitic diode, a technique may be considered in which the PLYC (512), which is the N-type in the memory cell area is converted into the P-type in a certain area of the CNT. However, if this technique is adopted, the number of steps of photo lithography and ion implantation increases and the steps become complicated. This leads reduction in yield of products.
On the other hand, in the second background art, the PLYD (514) is connected to the AL (516), which is the power line, at the side surface, as indicated by G of FIG. 20. Therefore, contact resistance varies considerably, and adversely affects properties of the products. The measurements of Vd-Id characteristics of the contact connected with the construction of FIG. 20 are shown in FIG. 21. Here, Vd is the voltage applied to the contact, and Id is the current flowing through the contact. It can be understood that Id varies greatly from 10.sup.-10 A to 10.sup.-6 A when Vd=0.1 V.
The present invention is made to solve the technical problems as described above, and has its object to provide a semiconductor memory device and a method of manufacturing the same which can solve the problem of penetration when other wiring layers are connected to thin film layers, and obtain a stable and sufficiently low contact resistance.